As is well known, an EEPROM (electrically erasable programmable read-only memory) is user-modifiable read-only memory that can be erased and reprogrammed repeatedly through the application of higher than normal electrical voltage. In general, EEPROM cells have proven to be a reliable and versatile form of nonvolatile reprogrammable memory.
FIG. 1 illustrates a conventional EEPROM device 100. The EEPROM includes a doped substrate 110 having an oxide layer 120 thereon. A polysilicon floating gate 130 is located over the oxide layer 120 and serves as both the gate of a transistor 140 and an electrode of the EEPROM. A control gate 150 is located over the floating gate 130 and separated therefrom by a dielectric layer 160.
Despite the success of EEPROM cells as a reliable and versatile form of nonvolatile reprogrammable memory, conventional EEPROM devices have their drawbacks. For example, the additional process steps required to form the second polysilicon or other conductive material layer comprising the control gate (150) add significant cost and time in fabricating the devices. Moreover, additional production costs are incurred when the process for manufacturing the EEPROMs can not be easily integrated with existing processes. Faced with ever increasing demands for smaller devices, higher yields at lower cost, and reduced production times, these additional processing steps are undesirable.
Previous attempts to alleviate these disadvantages included forming coplanar floating and control gates (130, 150) such that both gates could be formed in a single deposition step of the manufacturing process. However, while the resulting structure required fewer processing steps, these “single poly” EEPROM devices consumed large areas of the manufacturing wafer or die on which they were formed. This significantly increased area requirements and, therefore, limited the number of EEPROM devices fabricated on each die and increased the cost thereof. Thus, in addition to integration issues, EEPROM designers also face ever-increasing demands to decrease EEPROM surface area requirements.
Yet another issue that must be considered in addressing EEPROM manufacturing integration issues and decreasing EEPROM surface area requirements is maintaining an adequate coupling ratio. The coupling ratio (Cr) is given by the equation:Cr=Ccg—fg/(Ccg—fg+Cfg—sub)  (1)where Ccg—fg is the capacitance formed by the control gate of the EEPROM cell and the floating gate, and Cfg—sub is the capacitance formed by the floating gate and the substrate thereunder.
The coupling ratio Cr may also be given by the equation:
 Cr=Vfg/Vcg  (2)
where Vfg is the operating voltage of the floating gate and Vcg is the operating voltage of the control gate. The operating voltage required at the control gate Vcg to obtain the desired floating gate voltage is also known as the programming and/or erasure voltage. Typically, EEPROMs are designed to have a predetermined floating gate operating voltage Vfg. However, the voltage on the control gate Vcg depends on the coupling ratio Cr of the EEPROM device. It is highly desirable to keep the Vcg as low as possible to achieve robust performance and to keep the overall voltage requirements for the device as low as possible.
However, in view of Equation (2), an excessively small coupling ratio Cr arising from decreased size or simplified integration requires an increased control gate voltage Vcg. Moreover, in view of Equation (1), any excessive capacitance of Cfg—sub decreases the coupling ratio Cr such that, again, an increased control gate voltage Vcg is required in order to maintain the preferred floating gate voltage Vfg. Unfortunately, past attempts to simplify EEPROM manufacturing integration with CMOS integration, or to decrease surface area required of individual EEPROM cells, have exhibited a substantial Cfg—sub, that disadvantageously decreased the coupling ratio Cr and increased control gate voltage Vcg requirements, which as discussed above is a less than desirable design choice.
Accordingly, what is needed in the art is a semiconductor device that does not suffer from the deficiencies found in the prior art.